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some number of
shift halted
at least 8 clocks
enter error detect
command
optional clocks to
clock in 1s for testing
load fault
command
shift
resumed
exit error detect
command
CLK
SDI
shift_reg[n-1:0]
SDO
previous serial data shifting out
fault data
fault data MSB
this must be min. 2 μ s wide
and 3 clocks minimum with
output enable LOW
OE
LE
fault_load goes LOW
fault_load
fault_data[n-1:0]
on this edge of OE
fault data 8 bits
error_detect_mode
002aad208
Lower-case signal names are internal signals shown to aid understanding of timing.
Fig 9.
Timing for a complete error detection sequence